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preliminary cyw20710 single-chip bluetooth? transceiver and baseband processor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document no. 002-14804 rev. *h revised november 25, 2016 general description the cypress cyw20710 is a monolithic, single-chip, bluetooth 4. 0 compliant, stand-alone baseband processor with an integrated 2.4 ghz transceiver. manufactured using the industry's most advanced 65 nm cmos low-power process, the cyw20710 employs the highest level of integration, eliminati ng all critical external components, and thereby minimizing the device?s footprint a nd costs associated with the implementa tion of bluetooth solutions. the cyw20710 is the optimal solution for vo ice and data applications that require a bluetooth sig st andard host controller inte rface (hci) via uart h4 or h5 and pcm audio interface support. th e cyw20710 radio transceiver?s enhanced radio performance meets the most stringent industrial temperature application requirements for compact integr ation into mobile handset and portable dev ices. the cyw20710 is fully compatible with all standard tcxo frequencie s and provides full radio compatibility, enabling it to opera te simultaneously with gps and cellular radios. cypress part numbering scheme cypress is converting the acquired iot part numbers from cypress to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. table 1. mapping table for part number between broadcom and cypress features bluetooth 4.0 + edr compliant class 1 capable with built-in pa programmable output power control meets class 1, class 2, or class 3 requirements use supply voltages up to 5.5v supports cypress smartaudio?, wide-band speech, sbc codec, and packet loss concealment. fractional-n synthesizer s upports frequency refer- ences from 12 mhz to 52 mhz automatic frequency detection for standard crystal and tcxo values when an external 32.768 khz reference clock is provided. ultra-low power consumption supports serial flash interfaces available in 42-bump wlbga and 50-ball fpbga packages. arm7tdmi-s??based microprocessor with integrated rom and ram supports mobile without external memory applications mobile handsets and smart phones personal digital assistants automotive telematic systems broadcom part number cypress part number bcm20710 cyw20710 bcm20710a1kufbxg CYW20710A1KUFBXG bcm20710a1kubxg cyw20710a1kubxg
document no. 002-14804 rev. *h page 2 of 50 preliminary cyw20710 figure 1. functional block diagram cyw20710 microprocessor and memory unit (upu) bluetooth baseband core (bbc) high-speed peripheral transport unit (ptu) radio transceiver tcxo lpo pcm uart gpio memory spi i 2 s
document no. 002-14804 rev. *h page 3 of 50 preliminary cyw20710 contents 1. overview ............................................................ 4 1.1 major features .................................................... 4 1.2 block diagram ..................................................... 6 1.3 mobile phone usage model ................................ 7 2. integrated radio transceiver .......................... 8 2.1 transmitter path .................................................. 8 2.1.1 digital modulator ...................................... 8 2.1.2 power amplifier ....................................... 8 2.2 receiver path ...................................................... 8 2.2.1 digital demodulator and bit synchronizer 8 2.2.2 receiver signal stre ngth indicator .......... 8 2.3 local oscillator generation ................................. 8 2.4 calibration ........................................................... 9 2.5 internal ldo regulator ....................................... 9 3. bluetooth baseband core.............................. 10 3.1 transmit and receive func tions ......... .............. 10 3.2 bluetooth 4.0 + edr features .......................... 10 3.3 frequency hopping generat or ............ .............. 11 3.4 link control layer ............................................. 11 3.5 test mode support ....... .............. .............. ......... 11 3.6 power management unit . .............. ........... ......... 12 3.6.1 rf power management .............. ........... 12 3.6.2 host controller power management ..... 12 3.6.3 bluetooth baseband core power management .......................................... 13 3.7 adaptive frequency hoppi ng .............. .............. 14 3.8 collaborative coexistence ................................ 14 3.9 serial enhanced coexistence interface ............ 14 3.9.1 seci advantages .................................. 14 3.9.2 seci i/o ................................................ 14 4. microprocessor unit ....................................... 15 4.1 nvram configuration data and storage .......... 15 4.1.1 serial interface ...................................... 15 4.2 eeprom ..... ............... .............. .............. ........... 15 4.3 external reset ................................................... 15 4.4 one-time programmable memory .................... 16 4.4.1 contents ................................................ 16 4.4.2 programming ......................................... 16 5. peripheral transport unit .............................. 17 5.1 pcm interface ....................................................17 5.1.1 system diagram .....................................17 5.1.2 slot mapping ...........................................17 5.1.3 wideband speech ..................................18 5.1.4 frame synchronization ...........................18 5.1.5 data formatting ......................................18 5.2 hci transport detection configuration ..............19 5.3 uart interface ..................................................19 5.3.1 hci 3-wire transport (uart h5) ...........19 5.4 spi .....................................................................20 6. frequency references ................................... 21 6.1 crystal interface and cl ock generation .............21 6.2 crystal oscillator ................................................22 6.3 external frequency reference ..........................22 6.3.1 tcxo clock request support ................23 6.4 frequency selection ..........................................24 6.5 frequency trimming ..........................................24 6.6 lpo clock interface ...........................................25 7. pin-out and signal descriptions ................... 26 7.1 pin descriptions .................................................26 8. ball grid arrays .............................................. 28 9. electrical characteristics............................... 30 9.1 rf specifications ...............................................35 9.2 timing and ac characterist ics ........ ........... ........38 9.2.1 startup timing ........................................38 9.2.2 uart timing ..........................................39 9.2.3 pcm interface timing .............................40 9.2.4 bsc interface timing .............................44 10. mechanical information.. ................................ 45 10.1 tape, reel, and packing specification ..............47 11. ordering information...................................... 48 12. additional information ................................... 48 12.1 acronyms and abbreviations .............................48 12.2 iot resources ....................................................48 document history page ................................................. 49 sales, solutions, and legal information ...................... 50
document no. 002-14804 rev. *h page 4 of 50 preliminary cyw20710 1. overview the cypress cyw20710 complies with the blue tooth core specification, version 4.0 and is designed for use with a standard host controller interface (hci) uart. the combinat ion of the bluetooth baseband core (bbc), a peripheral transport unit (ptu), and a n arm ? -based microprocessor with on-chip rom provides a complete lower layer bluetooth protocol stack, including the link controller (lc), link manager (lm), and hci. 1.1 major features major features of the cyw20710 include: support for bluetooth 4.0 + edr, including the following options: ? a whitelist size of 25. ? enhanced power control ? hci read encryption key size command full support for bluetooth 2.1 + edr additional features: ? secure simple pairing (ssp) ? encryption pause resume (epr) ? enhance inquiry response (eir) ? link supervision time out (lsto) ? sniff subrating (ssr) ? erroneous data (ed) ? packet boundary flag (pbf) built-in low drop-out (ldo) regulators (2) ? 1.63 to 5.5v input voltage range ? 1.8 to 3.3v intermediate programmable output voltage integrated rf section ? single-ended, 50 ohm rf interface ? built-in tx/rx switch functionality ? tx class 1 output power capability ? -88 dbm rx sensitivity basic rate supports maximum bluetooth data rates over hci uart and spi interfaces multipoint operation, wit h up to 7 active slaves ? maximum of 7 simultaneous active acl links ? maximum of 3 simultaneous active sco and esco links, with scatternet support scatternet operation, with up to 4 active picone ts (with background scan and support for scattermode) high-speed hci uart transport support ? h4 five-wire uart (four signal wires, one ground wire) ? h5 three-wire uart (two signal wires, one ground wire) ? maximum uart baud rates of 4 mbps ? low-power out-of-band bt_w ake and host_wake signaling ? vsc from host transport to uart ? proprietary compressing scheme (allows more than two simultaneous a2dp packets and up to five devices at a time) channel quality-driven data rate (cqddr) and packet type selection standard bluetooth test modes extended radio and production test mode features
document no. 002-14804 rev. *h page 5 of 50 preliminary cyw20710 full support for po wer savings modes: ? bluetooth standard hold and sniff ? deep sleep modes and regulator shutdown supports wide-band speech (wbs) over pcm and packet loss concealment (plc) for better audio quality 2-, 3-, and 4-wire coexistence power amplifier (pa) shutdown for externa lly controlled coexistence, such as wimax built-in lpo clock or operation using an external lpo clock tcxo input and auto-detection of all st andard handset clock frequencies (supports low-power crystal, which can be used during power saving mode with better timing accuracy) or gate for combining a host clock request with a bluetooth clock request (operates even when the bluetooth core logic is power ed off) larger patch ram space to support future enhancements serial flash interface with native suppor t for devices from several manufacturers one-time programmable (otp) memory
document no. 002-14804 rev. *h page 6 of 50 preliminary cyw20710 1.2 block diagram figure 2 shows the interconnect of the ma jor cyw20710 physical blocks and associated external interfaces. figure 2. functional block diagram arm7tdmi \ s dma scan ? jtag address ? decoder bus ? arb trap ? & ? patch ahb2apb wd ? timer remap ? & ? pause 32 \ bit ? apb 32 \ bit ? ahb ahb2mem ahb2ebi external ? bus ? i/f rom 384 ? kb ahb2mem ram 112 ? kb pmu ? control uart debug ? uart ptu i/o ? port ? control pmu lpo por buffer apu bt ? clk/ hopper blue ? rf ? i/f rx/tx buffer digital ? modulator calibration ? & ? control digital ? demod ? bit ? sync bluetooth ? radio rf flash ? i/f jtag digital i/o spi/empspi (spiffy) i2c_master interrupt ? controller pcm usb gpio+aux sw ? timers jtag ? master lcu fifo ? 1 fifo ? 2 otp (128 ? bytes) spim seci coex low ? power ? scan blue ? rf ? registers
document no. 002-14804 rev. *h page 7 of 50 preliminary cyw20710 1.3 mobile phone usage model the cyw20710 is designed to provide a direct interfac e to new and existing handset designs, as shown in figure 3 . the device has flexible pcm and uart interfaces, enabling it to transparently co nnect to existing circuits. in addition, the tcxo and external lpo inputs allow the use of existing handset features, hel ping to minimize product size, power, and cost. the device incorporates a number of unique features to accommodate integration into mobile phone platforms. the pcm interface provides multiple modes of operation to support both master and slave, as well as hybrid interfacing to one o r more external codec devices. the uart interface supports hardware flow control with tight integration to power control si deband signaling to support the low est power operation. the tcxo interface accommodates the typica l reference frequencies used by cell phones. a programmable tcxo power-up or power-down signal (active-high or active-low) allows the device to indicate when the clock supplied to the device can be disabled for added power saving during sleep mode. the tcxo and external lpo inputs are hi gh-impedance with minimal loading on the driving source whether power is applied to the device or has been removed. the highly linear design of the radio transceiver ensures that t he device has the lowest output spurious emissions, regardless of the state of operation, and has been fully characterized in the global cellular bands. the transceiver design has excellent blocking (eliminating desensi tization of the bluetooth receiver) and intermodulation perfo r- mance (distortion of the transmitt ed signal caused by mixing the cellular and blue tooth transmissions) in the presence of a cel lular transmission (gsm, gprs, cdma, wcdma, or iden). minimal exter nal filtering is required for integration within the handset. few external components are required for integration and very compact wlbga packaging is available. figure 3. mobile phone usage model voice codec handset baseband tcxo lpo clock cyw20710 802.11 wlan uart/spi bt_wake host_wake clk_req lpo_input (optional) optional/status bt_busy/tx_req wifi_busy/tx_confirm xtal_in 1.63v to 5.5v battery pcm
document no. 002-14804 rev. *h page 8 of 50 preliminary cyw20710 2. integrated radio transceiver the cyw20710 has an integrated radio transce iver that has been optimized for use in 2.4 ghz bluetoot h wireless systems. it has been designed to provide low-power, low-cost, robust communicati ons for applications operating in the globally available 2.4 ghz unlicensed ism band. the cyw20710 is fully compliant with the bluetooth radio specif ication and enhanced data rate specificatio n and meets or exceeds the requirements to provide the highest communication link quality of service. 2.1 transmitter path the cyw20710 features a fully integrated zero if transmitter. the baseband transmitted data is digitally modulated in the modem block and up-converted to the 2.4 ghz ism band in the transmitter pa th. the transmitter path consists of signal filtering, i/q u p- conversion, a high-output power amplifier (pa), and rf filtering. the cyw20710 also incorporates modulation schemes to support enhanced data rates. p/4-dqpsk for 2 mbps 8-dpsk for 3 mbps 2.1.1 digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4dqpsk, and 8-dpsk signals. the fully digital modulator minimizes any frequency drift or anomalies in th e modulation characteristics of the transmitted signal and is much more stable than direct vco modulation schemes. 2.1.2 power amplifier the cyw20710 has an integrated pa that can be configured for cla ss 2 operation, transmitting up to +4 dbm. the pa can also be configured for class 1 operation, transmitting up +10 dbm at the chip in gfsk mode, when a minimum supply voltage of 2.5v is ap plied to vddtf. because of the linear nature of the pa, combi ned with integrated filtering, minimal ex ternal filtering is required to meet blue tooth and regulatory harmonic and spurious requirements. using a highly linearized, temperature comp ensated design, the pa can transmit +10 dbm for basic rate and +8 dbm for enhanced data rates (2 to 3 mbps). a flexible supply voltage range allows the pa to operate from 1.2v to 3.3v. a minimum supply voltage of 2.5v is required at vddtf to ac hieve +10 dbm of transmit power. 2.2 receiver path the receiver path uses a low if scheme to downconvert the re ceived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz is m band. the front-end topology, with built-in out-of-band attenuat ion, enables the device to be used in most applications without off-ch ip filtering. for integrated han dset operation where the bluet ooth function is integrated close to the cellula r transmitter, minimal external filtering is required to elimin ate the desensitizati on of the receiver by the cellular transmit signal. 2.2.1 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer uses the low if received signal to perform an optimal frequency tracking and bit s ynchro- nization algorithm. 2.2.2 receiver signal strength indicator the cyw20710 radio provides a receiver si gnal strength indicator (rssi) signal to the baseband so that the controller can take part in a bluetooth power-controlled link by providin g a metric of its own receiver signal strength to determine whether the transmi tter should increase or decrease its output power. 2.3 local oscillator generation local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immuni ty to lo pulling during pa operation. the device uses fully- integrated pll loop filters.
document no. 002-14804 rev. *h page 9 of 50 preliminary cyw20710 2.4 calibration the radio transceiver features an automated calibration scheme that is fully self-contain ed in the radio. user interaction is n ot required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the performance of al l major blocks in the radio, including gain and phase characteristi cs of filters, matching between key components, and key gain b locks. calibration, which takes process and temperat ure variations into account, occurs trans parently during the settling time of the hops, adjusting for temperature variations as the device cools and heats during normal operation. 2.5 internal ldo regulator two internal low drop-out (ldo) voltage regulators eliminate the need for external voltage regul ators and therefore reduce the bom. the first ldo is a preregulator (hv ldo). the second ldo (main ldo) supplies the main power to the cyw20710 (see figure 2 ). the hv ldo has an input voltage range of 2. 3v to 5.5v. the input vbat is ideal for batteries. the vreghv output is programmable from 1.8v to 3.3v, in 100 mv steps. the dropout voltage is 200 mv. the hv ldo can supply up to 95 ma, which leaves spare power for external circuitry such as an rf power amp for higher transmit power. if the hv ldo is not used , to turn off the hv ldo and minimize current consumption, connect the vbat input to the vreghv output. firmware can then disable the hv ldo, saving the quiescent current. the hv ldo default output voltage is 2.9v, allowing this regulator to be used to power external nv memory devices, as well as t he vddo rail. the firmware can then adjust this output to as low as 1.8v, if desired, to power vddtf. the main ldo has a 1.22v output (vreg) and is used to supply main power to the cyw20710. the input of this ldo (vreghv) has an input voltage range of from 1.63v to 3.63v. the output of the hv ldo is inter nally connected to the input to the main ld o. power can be applied to vreghv when the hv ldo is not used. the main ldo supplies power to the entire device for class 2 operation. the main ldo can drive up to 60 ma, which leaves sp are power for external circuitry. the main ldo is bypassed by not connecting anything to its output (vreg) and driving 1.12v?1.32v directly to vddc and vddrf. reg_en provides a control signal for the host to control power to the cyw20710. when power is enabled, the cyw20710 will requir e complete initialization. figure 4. ldo functional block diagram cyw20710 hv ldo main ldo vreghv vbat vreg reg_en
document no. 002-14804 rev. *h page 10 of 50 preliminary cyw20710 3. bluetooth baseband core the bluetooth baseband core (bbc) implements the time critical functions required fo r high-performance bluetooth operation. the bbc manages buffering, segmentation, and data routing for all co nnections. it also buffers data that passes through it, handles data flow control, schedules sco/acl tx/rx tran sactions, monitors bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and compos es and decodes hci packets. in addition to these functions, i t independently handles hci event types and hci command types. 3.1 transmit and receive functions the following transmit and receive functions are implemented in t he bbc hardware to increase the reliability and security of th e tx/ rx data before sending the data over the air: in the transmitter: data framing forward error correction (fec) generation header error control (hec) generation cyclic redundancy check (crc) generation key generation data encryption data whitening in the receiver: symbol timing recovery data deframing fec hec crc data decryption data dewhitening 3.2 bluetooth 4.0 + edr features the cyw20710 supports bluetooth 4.0 + edr, including the following options: a whitelist size of 25 enhanced power control hci read encryption key size command the cyw20710 provides full support for bl uetooth 2.1 + edr a dditional features: secure simple pairing (ssp) encryption pause resume (epr) enhance inquiry response (eir) link supervision time out (lsto) sniff subrating (ssr) erroneous data (ed) packet boundary flag (pbf)
document no. 002-14804 rev. *h page 11 of 50 preliminary cyw20710 3.3 frequency hopping generator the frequency hopping sequence generator selects the correct hopping channel number, based on the link controller state, blueto oth clock, and device address. 3.4 link control layer the link control layer is part of the blue tooth link control functions im plemented in dedicated logic in the link control unit (lcu). this layer consists of the command controller that takes comm ands from the software and other controllers that are activated or configured by the command controll er to perform the link control tasks. there are two major states?standby and con nection. each task establishes a different st ate in the bluetooth link controller. in addition, there are eight substates?page, page scan, in quiry, inquiry scan, park, sniff subrate, and hold. 3.5 test mode support the cyw20710 fully supports bluetooth test mode, including the transmitter tests, normal and delayed loopback tests, and the reduced hopping sequence. in addition to the standard bluetooth test mode, the device supports enhanced testin g features to simplify rf debugging and qua li- fication and type approval testing. these test features include: fixed frequency carrier wave (unmodulated) transmission ? simplifies some type approval measurements (japan) ? aids in transmitter performance analysis fixed frequency constant receiver mode ? directs receiver output to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissi ons testing for receive mode fixed frequency constant bit stream transmission ? unmodulated, 8-bit fixed pattern, prbs-9, or prbs-15 ? enables modulated signal measurements with standard rf test equipment packetized connectionless transmitter test ? hopping or fixed frequency ? multiple packet types supported ? multiple data patterns supported packetized connectionless receiver test ? fixed frequency ? multiple packet types supported ? multiple data patterns supported
document no. 002-14804 rev. *h page 12 of 50 preliminary cyw20710 3.6 power management unit the power management unit (pmu) provides power management features that can be in voked through power management registers or packet handling in the baseband core. this section contains descriptions of the pmu features. 3.6.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver. the transceiver then processes the power-down functions, accordingly. 3.6.2 host controller power management the host can place the device in a sleep state, in which all nonessential blocks ar e powered off and all nonessential clocks ar e disabled. power to the digital core is maintained so that the state of the registers and ram is not lost. in addition, the lpo clock is applied to the internal sleep controller so that the chip can wa ke automatically at a specified time or based on signaling from the host. the goal is to limit the current consumption to a minimum, while maintaining t he ability to wake up and resume a connection wit h minimal latency. if a scan or sniff session is enabled while the device is in sleep mode, the device automatically will wake up for the scan/sni ff event, then go back to sleep when the event is done. in this case, the device uses its internal lpo-based timers to trigger the period ic wake up. while in sleep mode, the transports are idle. however, the host can signal the device to wake up at any time. if signaled t o wake up while a scan or sniff session is in progress, the session co ntinues but the device will not sleep between scan/sniff events. once sleep mode is enabled, the wake signaling mechanism can also be thought of as a sleep signaling mechanism, since removing the wake status will often ca use the device to sleep. in addition to a bluetooth device wake signaling mechanism, ther e is a host wake signaling mechanism. this feature provides a w ay for the bluetooth device to wake up a host that is in a reduced power state. there are two mechanisms for the device and the host to signal wake status to each other: when running in spi mode, the cyw20710 has a mode where it ente rs sleep mode when there is no activity on the spi interface for a specified (programmable) amount of time. idle mode is detect ed when the spi_csn is left deasse rted. whether to sleep on an id le interface and the amount of time to wait before entering sleep mode can be program ed by the host. once the cyw20710 enters sleep, the host can wake it by asserting spi_csn. if the host decides to sleep, th e cyw20710 will wake up the host by asserting spi_int when it has data for it. note: successful operation of the power manag ement handshaking signals requires coordinated support between the device firmware and the host software. bluetooth wake (bt_wake) and host wake (and host_wake) signaling the bt_wake pin (gpio_0) allows the host to wa ke the bt device, and host_wake (gpio_1) is an out put that allows the bt device to wake the host. in-band uart signaling the cts and rts signals of the uart interface are used for bt wake (cts) and host wake (rts) functions in addition to their normal function on the uart interface. note that this applies for both h4 and h5 protocols.
document no. 002-14804 rev. *h page 13 of 50 preliminary cyw20710 3.6.3 bluetooth baseband core power management the device provides the following low-power oper ations for the bluetooth baseband core (bbc): physical layer packet handling turns rf on and off dynamically within packet tx and rx. bluetooth specified low-power connection modes?sniff, hold, and park. while in these low-power connection modes, the device runs on the low power oscillator and wakes up after a predefined time period. backdrive protection the cyw20710 provides a backdrive protection feature that allows the device to be turned off while the host and other devices i n the system remain operati onal. when the device is no t needed in the system, v dd_rf and vddc are shut down and vddo remains powered. this allows the device to be effectively off, while ke eping the i/o pins powered so that they do not draw extra curren t from other devices connected to the i/o. note: vdd_rf collectively refers to the vddtf, vddif, vddlna, vddpx, and vddrf rf power supplies. note: never apply voltage to i/o pins if vddo is not applied. during the low power shutdown state and as long as vddo remains applied to the device , all outputs are tristated and all digita l and analog clocks are disabled. input voltages must remain within t he limits defined for normal operatio n. this is done to either p revent current draw and back loading on digital signals in the system. it also enables the device to be fully integrated in an embedde d device and take full advantage of the lowest power savings modes. if v ddc is powered up externally (not connected to vreg), vddc requires 750k ohms to ground during low-power shutdown. if v ddc is powered up by vreg, vddc does not require 750k ohms to ground because the internal main ldo has about 750 k ohms to ground when turned off. several signals, including the frequency reference input (xtal_in ) and external lpo input (lpo_in), are designed to be high- impedance inputs that will not load down the driving signal, even if vddo power is not applied to the chip. the other signals w ith back drive prevention are rst_n, coex_out0, coex_out1, coex_in , pcm_sync, pcm_clk, pcm_out, pcm_in, uart_rts_n, uart_cts_n, uart_rxd, uart_txd, gpio_0, gpio_1 , gpio_2, gpio_4, gpio_7, cfg_sel, and otp_dis. all other io signals must remain at vss until vddo is applied. failing to do this can result in unreliable startup behavior. when powered on, using reg_en is the same as applying power to the cyw20710. the device does not have information about its state before being powered-down. table 2. power control pin summary pin direction description bt_wake (gpio_0) host output bt input bluetooth device wake-up: signal from the host to the bluetooth device that the host requires attention. ? asserted = bluetooth device must wake up or remain awake. ? deasserted = bluetooth device may sl eep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. by default, bt_wake is active-low (if bt-wake is lo w it requires the device to wake up or remain awake). host_wake (gpio_1) bt output host input host wake-up. signal from the bluetooth devi ce to the host indica ting that bluetooth device requires attention. ? asserted = host device must wake up or remain awake. ? deasserted = host device may sleep when sleep criteria are met. the polarity of this signal is software c onfigurable and can be asserted high or low. clk_req (gpio_5) bt output clock request ? asserted = external clock reference required ? deasserted = external clock reference may be powered down the polarity of clk_req is software configurable and can be set to active high (tm0 = 1) or active low (tm0 = 0). reg_en bt input enables the internal preregulator and main regulator outputs. reg_en is active-high. ? 1 = enabled ? 0 = disabled
document no. 002-14804 rev. *h page 14 of 50 preliminary cyw20710 3.7 adaptive frequency hopping the cyw20710 supports host channel classification and dynamic channel classification adaptive frequency hopping (afh) schemes, as defined in t he bluetooth specification. host channel classification enables the host to set a predefined hopping map for the device to follow. if dynamic channel classification is enabled, the device gathers link quality statistics on a channel-by-channel basis to facil itate channel assessment and channel map selection. to provide a more accura te frequency hop map, link quality is determined using both rf an d baseband signal processing. 3.8 collaborative coexistence the cyw20710 provides extensions and collaborative coexistence to the standard bluetooth afh fo r direct communication with wlan devices. collaborative coexistence enables wlan and bluet ooth to operate simultaneously in a single device. the device supports industry-standard coexistence si gnaling, including 802.15.2, and supports cypress and third-party wlan solutions. using a multitiered prioritization approach, relative priorities between data types and applicatio ns can be set. this approach maximizes the performance-wlan data throughput vs. voice quality vs. link performance. a pa shutdown pin is available to allow full external control of the rf output for other types of coexistence, such as wimax. 3.9 serial enhanced coexistence interface the serial enhanced coexistence interface (serial eci or seci) is a proprietary cypress interface between cypress wlan devices and bluetooth devices. it is an optional replacement to the lega cy 3- or 4-wire coexistence feat ure, which is also available. the following key features are associated with the interface: enhanced coexistence data can be exchanged over seci_in and seci_out. it supports generic uart communication between wlan and bluetooth devices. to conserve power, it is disabled when inactive. it supports automatic resynchroniza ton upon waking from sleep mode. it supports a baud rate of up to 4 mbps. 3.9.1 seci advantages the advantages of the seci over the le gacy 3-wire coexistence interface are: only two wires are required: seci_in and seci_out. up to 48-bits of coexistence data can be exchanged. previous cypress stand-alone bluetooth devi ces such as the cyw2070 supported only a 3- wire or 4-wire coex istence interface. previous cypress wlan and bluetooth combination devices such as the cyw4325, cyw4329, and cyw4330 support an internal parallel enhanced coexistence interface for more efficient wl an and bluetooth information exchange. the seci allows enhanced coexistence information to be passed to a companion cypress wlan chip through a serial interface using fewer i/o than the 3-wir e coexistence scheme. the 48-bits of the seci significantly enhance wlan and bluetooth coexistence by sharing such information as frequencies used an d radio usage times. the exact contents of the seci are cypress confidential. 3.9.2 seci i/o the cyw20710 does not have dedicated seci_in or seci_out pins, but the two pin functions can be mapped to the following digital i/o: the uart, gpio, spim (or bsc), pcm, and coex pins. pin function mapping is controlled by the config file that is either st ored in nvram or downloaded directly into on-chip ram from the host.
document no. 002-14804 rev. *h page 15 of 50 preliminary cyw20710 4. microprocessor unit the cyw20710 microprocessor unit runs software from the link cont rol (lc) layer up to the host controller interf ace (hci). the microprocessor is based on the arm7tdmis 32-bit risc proce ssor with embedded ice-rt debug and jtag interface units. the microprocessor also includes 384 kb of rom memory for program storage and boot rom, 112 kb of ram for data scratch-pad, and patch ram code. the internal boot rom provides flexibility during power-on reset to enable the same device to be used in various configurations , including automatic host transport selection from spi or uart, wit h or without external nvram. at power-up, the lower layer pro tocol stack is executed from the internal rom. external patches can be applied to the rom-based firmware to pr ovide flexibility for bug fixes and features additions. these pa tches can be downloaded from the host to the device through the spi or uart transports, or us ing external nvram. the device can also support the integration of user applications and profiles using an external serial flash memory. 4.1 nvram configuration data and storage 4.1.1 serial interface the cyw20710 includes an spi master controller that can be used to access serial flash memory. the spi master contains an ahb slave interface, transmit and receive fifos, and the spi core phy logic. data is transferred to and from the module by the syst em cpu. dma operation is not supported. the cyw20710 supports serial flash vendors atmel, mxic, and num onyx. the most commonly used part s from two of these vendors are: at25bcm512b, manufactured by atmel mx25v512zui-20g, manufactured by mxic 4.2 eeprom the cyw20710 includes a broadcom? serial control (bsc) master in terface. the bsc interface supports low-speed and fast mode devices and is compatible with i 2 c slave devices. multiple i 2 c master devices and flexible wait st ate insertion by the master interface or slave devices are not supported. the cyw 20710 provides 400 khz, full speed clock support. the bsc interface is programmed by the cpu to gene rate the following bsc transfer types on the bus: read-only write-only combined read/write combined write-read nvram may contain configuration information about the customer applicatio n, including the following: fractional-n information bd_addr uart baud rate sdp service record file system information used for code, code patches, or data 4.3 external reset the cyw20710 has an integrated power-on reset circuit which complete ly resets all circuits to a kn own power on state. this acti on can also be driven by an external reset signal, which can be us ed to externally control the device, forcing it into a power-on reset state. the rst_n signal input is an active-low signal for all versions of the cyw20710. the cyw20710 requires an external pull-up resi stor on the rst_n input. alternatively, the rst_n input can be co nnected to reg_en or driven directly by a host gpio.
document no. 002-14804 rev. *h page 16 of 50 preliminary cyw20710 4.4 one-time programmable memory the cyw20710 includes a one-time programmable (otp) memory , allowing manufacturing customization and avoiding the need for an on-board nvram.if customization is not required, then the otp does not need to be programmed. whether the otp is programmed or not, it is disabled after th e boot process completes to save power. the otp size is 128 bytes. the otp is designed to store a minimal amount of information. aside from otp data, most user configuration information will be downloaded into ram after the cyw20710 boots up and is ready for ho st transport communication. th e otp contents are limited to: parameters required prior to downloading user configuration to ram. parameters unique to a customer design. 4.4.1 contents the following are typical parameters programmed into the otp memory: bd_addr software license key output power calibration frequency trimming initial status led drive configuration the otp contents also include a static error correction table to improve yield during the programming process as well as forwar d error correction codes to eliminate any long-term reliability problems. the otp contents as sociated with error correction are not vis ible by customers. 4.4.2 programming otp memory programming takes place through a combination of cy press software integrated with the manufacturing test software and code embedded in cyw20710 firmware. programming the otp requires a 3.3v supply. the otp programming supply comes from the vddo pin. the otp power supply can be as low as 1.8v in order to read the ot p contents. otp_dis is brought out to a pin on the wlbga package but not on the fpbga package, and is internally pulled low. if the otp_dis pin is left floating or externally pulled low, then the otp will be enabl ed. if the otp_dis pins is externally pulled high, then the otp will be disabled.
document no. 002-14804 rev. *h page 17 of 50 preliminary cyw20710 5. peripheral transport unit this section discusses the pcm, uart, and spi peripheral interfac es. the cyw20710 has a 1040 byte transmit and receive fifo, which is large enough to hold the entire pa yload of the largest edr bt packet (3-dh5). 5.1 pcm interface the cyw20710 pcm interface can connect to linear pcm codec devic es in master or slave mode . in master mode, the device generates the pcm_bclk and pcm_sync signals. in slave mode, these signals are provided by another master on the pcm interface as inputs to the device. the device supports up to three sco or esco channels thro ugh the pcm interface and each channel can be independently mapped to any available slot in a frame. the host can adjust the pcm interf ace configuration using vendor-specific hci comm ands or it can be setup in the configuration file. 5.1.1 system diagram figure 5 shows options for connecting the device to a pcm codec device as a master or a slave. figure 5. pcm interface with linear pcm codec 5.1.2 slot mapping the device supports up to three simultaneous, full-duplex sco or esco channels. these channels are time-multiplexed onto the pcm interface using a time slotting scheme based on the audio sampling rate, as described in ta b l e 3 . pcm interface slave mode pcm codec (master) cyw20710 (slave) pcm_in pcm_bclk pcm_sync pcm_out pcm interface master mode pcm codec (slave) cyw20710 (master) pcm_in pcm_bclk pcm_sync pcm_out pcm interface hybrid mode pcm codec (hybrid) cyw20710 (hybrid) pcm_in pcm_bclk pcm_sync pcm_out
document no. 002-14804 rev. *h page 18 of 50 preliminary cyw20710 transmit and receive pcm data from an sco channel is always mappe d to the same slot. the pcm data output driver tri-states its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tri-states its ou tput after the falling edge of the pcm clock during the last bit of the slot. 5.1.3 wideband speech the cyw20710 provides support for wideband speech (wbs) in two ways: transparent mode the host encodes wbs packets and the encoded packets are transferred over the pcm bus for sco or esco voice connections. in transparent mode, the pcm bus is typically configured in master mode for a 4 khz sync rate with 16-bit samples, resulting in a 64 kbps bit rate. on-chip smartaudio? technologythe cyw20710 can perform s ubband-codec (sbc) encoding and decoding of linear 16 bits at 16 khz (256 kbps rate) transferred over the pcm bus. 5.1.4 frame synchronization the device supports both short and long frame synchronization types in both master and slave co nfigurations. in short frame syn chro- nization mode, the frame synchronization signal is an active-high pulse at the 8 khz audio frame rate (which is a single bit per iod in width) and synchronized to the rising edge of the bit clock. th e pcm slave expects pcm_sync to be high on the falling edge of t he bit clock and the first bit of the first slot to start at the next rising edge of the clock. in the long frame synchronization mode, the frame synchronization signal is an active-high pulse at the 8 khz audi o frame rate. however, the duration is 3-bit periods and the pul se starts coincident with the first bit of the first slot. 5.1.5 data formatting the device can be configured to generate and accept several differ ent data formats. the device uses 13 of the 16 bits in each p cm frame. the location and order of these 13 bi ts is configurable to support various data formats on the pcm interface. the remain ing three bits are ignored on the input, and may be filled with zero s, ones, a sign bit, or a programmed value on the output. the d efault format is 13-bit two?s complement data, left justified, and clocked most significant bit first. table 3. pcm interface time slotting scheme audio sample rate time slotting scheme 8 khz the number of slots depends on the selected interface rate, as follows: interface ? rate slot 128 1 256 2 512 4 1024 8 2048 16 16 khz the number of slots depends on the selected interface rate, as follows: interface ? rate slot 256 1 512 2 1024 4 2048 8
document no. 002-14804 rev. *h page 19 of 50 preliminary cyw20710 5.2 hci transport detection configuration the cyw20710 supports the following interface types for the hci transport from the host: uart (h4 and h5) spi only one host interface can be active at a time. the firmware pe rforms a transport detect function at boot-time to determine wh ich host is the active transport. it can auto-detect the uart inte rface, but the spi interface must be selected by strapping the sc l pin to 0. the complete algorithm is summarized as follows: 1. determine if scl is pulled low. if it is, select spi as hci host transport. 2. determine if any local nvram contains a valid configuration f ile. if it does and a transport configuration entry is present, select the active transport according to entry, and then exit the transport detection routine. 3. look for cts_n = 0 on the uart interfac e. if it is present, select uart. 4. repeat step 3 until transport is determined. 5.3 uart interface the uart physical interface is a standard, 4-wire interface (rx, tx, rts, cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the interface features an au tomatic baud rate detection capability that return s a baud rate selectio n. alternatively, the baud rate can be selected via a vendor-specific uart hci command. the interface supports bl uetooth uart hci (h4) specifications. the default baud rate for h4 is 115.2 kbaud. the following baud rates are supported: normally, the uart baud rate is set by a configuration record downloaded after reset or by automatic baud rate detection. the h ost does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is provided through a vendor-specific command. the cyw20710 uart operates with t he host uart correctly, provided the combined ba ud rate error of the two devices is within 2% . 5.3.1 hci 3-wire transport (uart h5) the cyw20710 supports h5 uart transport for serial uart commun ications. h5 reduces the number of signal lines required by eliminating cts and rts, when compared to h4. in addition, in-b and sleep signaling is supported over the same interface so that the 4-wire uart and the 2-wire sleep signalin g interface can be reduced to a 2-wire uart interface, saving four ios on the host . h5 requires the use of an external lpo. cts must be pulled low. 9600 115200 2000000 14400 230400 3000000 19200 460800 3250000 28800 921600 3692000 38400 1444444 4000000 57600 1500000
document no. 002-14804 rev. *h page 20 of 50 preliminary cyw20710 5.4 spi the cyw20710 supports a slave spi hci transport with an input clo ck range of up to 16 mhz. higher clock rates may be possible. the physical interface between the spi master and the cyw20710 cons ists of the four spi signals (spi_csb, spi_clk, spi_si, and spi_so) and one interrupt signal (spi_int). the cyw20710 can be configured to accept ac tive-low or active-high polarity on the spi_csb chip select signal. it can also be configured to drive an active-low or active-high spi_int interrupt signal. bit order ing on the spi_si and spi_so data lines can be co nfigured as either little-endian or big- endian. additionally, proprietary sleep mode, half- duplex handshaking is implemented betw een the spi master and the cyw20710. spi_int is required to negotiate the start of a transacti on. the spi interface does not requir e flow control in the middle of a payload. the fifo is large enough to handle the largest packet size. only the spi master can stop the flow of bytes on the data lines, s ince it controls spi_csb and spi_clk. flow control s hould be implemented in higher layer protocols.
document no. 002-14804 rev. *h page 21 of 50 preliminary cyw20710 6. frequency references the cyw20710 uses two different frequency references for norma l and low-power operational modes. an external crystal or frequency reference driven by a temperature compensated crystal oscillator (tcxo) si gnal is used to generate the radio frequenc ies and normal operation clocking. either an external 32.768 khz or fu lly integrated internal low-power oscillator (lpo) is used for low- power mode timing. 6.1 crystal interface and clock generation the cyw20710 uses a fractional-n synthesiz er to generate the radio frequencies, clo cks, and data/packet timing, enabling it to operate from any of a multitude of frequency sources. the source can be external , such as a tcxo, or a crystal interfaced direc tly to the device. the default frequency reference setting is for a 20 mhz crystal or tcxo. the signal characterist ics for the crystal interface a re listed in ta b l e 4 . table 4. crystal interface signal characteristics parameter crystal external frequency reference units acceptable frequencies 12?52 mhz in 2 ppm 1 steps 1. the frequency step size is ap proximately 80 hz resolution. 12?52 mhz in 2 ppm 1 steps ? crystal load capacitance 12 (typical) n/a pf esr 60 (max) ? ? power dissipation 200 (max) ? w input signal amplitude n/a 400 to 2000 2000 to 3300 (requires a 10 pf dc blocking capacitor to attenuate the signal) mvp-p signal type n/a square-wave or sine-wave ? input impedance n/a ? 1 ? 2 m ? pf phase noise @ 1 khz @ 10 khz @ 100 khz @ 1 mhz n/a n/a n/a n/a n/a ? < ?120 2 < ?131 2 < ?136 2 < ?136 2 2. with a 26 mhz reference clock. for a 13 mhz clock, subtract 6 db. for a 52 mhz clock, add 6 db. ? dbc/hz dbc/hz dbc/hz dbc/hz auto-detection frequencies when using external lpo 3 3. auto-detection of the frequency requires the crystal or exter nal frequency reference to have less than 50 ppm of variation an d also requires an external lpo frequency which has less than 250 ppm of variation at the time of detection. 12, 13, 14.4, 15.36, 16.2, 16.8, 18, 19.2, 19.44, 19.68, 19.8, 20, 24, 26, 33.6, 37.4, and 38.4 12, 13, 14.4, 15.36, 16.2, 16.8, 18, 19.2, 19.44, 19.68, 19.8, 20, 24, 26, 33.6, 37.4, and 38.4 mhz tolerance without frequency trimming 4 4. at-cut crystal or txco recommended. 20 20 ppm initial frequency tolerance trimming range 50 50 ppm
document no. 002-14804 rev. *h page 22 of 50 preliminary cyw20710 6.2 crystal oscillator the cyw20710 can use an external crystal to provide a frequency reference. the reco mmended configuration for the crystal oscill ator, including all external components, is shown in figure 6 . figure 6. recommended oscillator configuration 6.3 external frequency reference an external frequency reference generated by a tcxo signal that may be directly con nected to the crystal input pin on the cyw20 710, as shown in figure 7 . the external frequency reference input is designed to not change loading on the tcxo when the cyw20710 is powered up or powered down. when using the cyw20710 with the txco or gate option, gpio 6 mu st be driven active high or active low. excessive leakage current results if gpio6 is allowed to float. figure 7. recommended tcxo connection 0 to 18 pf* xin xout crystal oscillator *capacitor value range depends on the manufacturer of the xtal as well as board layout. 0 to 18 pf* no connection tcxo xin xout 10?1000 pf* * recommended value is 100 pf. higher values produce a longer startup time. lower values have greater isolation. larger values help small signal swings.
document no. 002-14804 rev. *h page 23 of 50 preliminary cyw20710 6.3.1 tcxo clock request support if the application utilizes an external tcxo as a clock reference, the cyw20710 provides a clock request output to allow the sy stem to power off the tcxo when not in use. optionally, some package s support a tcxo or function that allows a clock request in the system to be combined with the cyw20710 clock request out put, without requiring an extra component on the board. clock request output the clk_req signal on the gpio_5 lead is asserted whenever the cy w20710 is in the awake state. it is deasserted when in sleep state. when the cyw20710 is sleeping, it uses an lpo clock (external or internal) as the timing reference. the tm0 lead controls the polarity of t he clk_req output on gpio_5 as follows: tm0 = 0 clk_req is active low tm0 = 1 clk_req is active high if the clock request feature is not desired, gp io_5 can be configured for other functions. tcxo or option the cyw20710 has an optiona l feature that allows t he application to perform a l ogical or function on a system tcxo clock reques t signal and the cyw20710 clock request to form one clock request ou tput to the tcxo device. this logical or function is embedded in the pad ring so that it is available at any time, as long as the pad ring is receiving a vddo supply. the function works eve n if the cyw20710?s digital core is sleeping or completely powered off. to use this feature, the tcxo_mode lead must be tied high. in th is mode, the gpio_6 lead functi ons as the external clock reques t input. without tcxo_mode asserted, gpio_5 functions as the clock r equest output (based only on the internal clock requirements of the cyw20710) and the state of gpio_6 is ignored. as mentioned earlier, the tm0 lead controls the polarity of the clk_req output on gpio_5. however, it assumes that gpio_6 input polarity is already consistent with the desired polarity on gpio _5/clk_req. therefore, when tm0 is 1 for an active high output, the function is a simple or between the external gpio_6 and the intern al clock request state. however, when tm0 is 0 for an active low output, the logic inverts the internal clo ck request signal and performs an and betwe en it and the gpio_6 input. even though it is using an or gate, it still provides a logical and on the two clock request states. since the logic assumes that it is also active low (similar to gpio_5 output), it do es not invert the gpio_6 input first. ta b l e 5 shows the truth table. table 5. truth table gpio_6 clk_req_in internal clock request state (0 = sleep) tm0 (0 = active low output) gpio_5 clk_req 00 0 0 01 0 0 10 0 1 11 0 0 00 1 0 01 1 1 10 1 1 11 1 1
document no. 002-14804 rev. *h page 24 of 50 preliminary cyw20710 package options and tcxo mode only a few package options bring out tm0 to balls, allowing the a pplication to configure them. in most packages, these pins are already configured. ta b l e 6 lists available package options. 6.4 frequency selection any frequency within the range specified for the crystal and tcxo reference can be used. these frequencies include standard han dset reference frequencies (12, 13, 14.4, 15.36, 16.2, 16.8, 18, 19.2, 19.44, 19.68, 19.8, 20, 24, 26, 33.6, 37.4, and 38.4 mhz) and any frequency between these reference frequencies, as desired by the system designer. since bit timing is derived from the referenc e frequency, the cyw20710 must have the reference frequency set corr ectly in order for the uart and pcm interfaces to function properly. the cyw20710 reference frequency can be set in one of three ways. use the default 20 mhz frequency designate the reference frequency in external nvram auto-detect the standard handset reference frequencies using an external lpo clock the cyw20710 is set to a default frequency of 20 mhz at the fact ory. for a typical design using a crystal, it is recommended th at the default frequency be used, since this simplifies the design by removing the need for either external nvram or external lpo cloc k. if the application requires a frequency other than the default, the value can be stored in an external nvram. programming the reference frequency in nvram provides the maximum flexibility in the selection of the reference frequency, since any frequency within the specified range for crystal and external frequency reference can be used. during power-on reset (por), the device downloads the parameter settings stored in nvram, which can be programmed to include the reference frequency and frequency trim values. typically, this is how a pc bl uetooth application is configured. for applications such as handsets and portab le smart communication devices, where th e reference frequency is one of the standar d frequencies commonly used, the cyw20710 autom atically detects the reference frequency and programs itself to the correct reference frequency. in order for auto-frequency detection to work properly, the cyw20710 must have a valid and stable 32.768 kh z external lpo clock present during por. this eliminates the need fo r nvram in applications where the external lpo clock is avail able and an external nvram is typically not used. 6.5 frequency trimming the cyw20710 uses a fractional-n synthesizer to digitally fine-tune the frequency reference input to within 2 ppm tuning accur acy. this trimming function can be applied to either the crystal or an external frequency source such as a tcxo. unlike the typical crystal- trimming methods used, the cyw20710 changes the frequency using a fully digital implementation and is much more stable and unaffected by crystal characteristics or te mperature. input imp edance and loading characteristics remain unchanged on the tcxo or crystal during the trimming process and are unaf fected by process and temperature variations. the option to use or not use fr equency trimming is ba sed on the system designer?s cost tr ade-off between bi ll-of-materials (bom ) cost of the crystal and the added manufacturing cost associated wi th frequency trimming. the frequency trimming value can either be stored in the host and written to the cyw20710 as a vendor-spe cific hci command or stored in nvram and subsequently recalled during por. frequency trimming is not a substitute for the poor use of tuning capacitors at an crystal oscillator (xtal). occasionally, tri mming can help alleviate hardware changes. table 6. package options part number package description tm0 CYW20710A1KUFBXG 50-ball fpbga, optimized fo r cell phone applications brought to ball cyw20710a1kubxg 42-ball wlbga 1
document no. 002-14804 rev. *h page 25 of 50 preliminary cyw20710 6.6 lpo clock interface the lpo clock is the second frequency reference that the cyw20710 us es to provide low-power mode timing for park, hold, and sni ff. the lpo clock can be provided to the device externally, from a 32. 768 khz source or the cyw20710 can operate using the internal lpo clock. the lpo can be internally driven from the main clock. however, sleep current will be impacted. the accuracy of the internal lpo limits the maximum park, hold, and sniff intervals. table 7. external lpo signal requirements parameter external lpo clock units nominal input frequency 32.768 khz frequency accuracy 250 ppm input signal amplitude 200 to 3600 mvp-p signal type square-wave or sine-wave ? input impedance (when power is applied or power is off) >100 <5 k ? pf
document no. 002-14804 rev. *h page 26 of 50 preliminary cyw20710 7. pin-out and signal descriptions 7.1 pin descriptions table 8. cyw20710 signal descriptions signal fpbga 50-ball wlbga 42-bump i/o power domain description radio res g4 d6 o vdd_rf external calibration resistor, 15 k ? @ 1% rfp d1 c7 i/o vdd_rf rf i/o antenna port xin g2 f5 i vdd_rf crystal or reference input xout g3 e5 o vdd_rf crystal oscillator output analog lpo_in a4 b4 i vddrf external lpo input voltage regulators reg_en b2 b5 i vddo hv ldo and main enable vbat a3 a5 i n/a hv ldo input vreghv a2 a6 i/o n/a hv ldo output: main ldo input vreg a1 a7 o n/a main ldo output straps rst_n b4 c5 i vddo active-low reset input tm0 c4 ? i vddo clock request polarity select tm1 ? ? i vddo internally connected to ground tm2 f3 c6 i vddo reserved: connect to ground. digital i/o gpio_0 b5 c3 i/o vddo gpio/bt_wake gpio_1 b3 b3 i/o vddo gpio/host_wake gpio_2 ? ? i/o vddo gpio gpio_3 ? ? i/o vddo gpio/link_ind note: can be configured for active high or low as well as open drain. gpio_4 ? ? i/o vddo gpio gpio_5 e6 f4 i/o vddo gpio/clk_req tcxo-or function out available on some packages. see section 11.?ordering information? . gpio_6 e3 d5 i/o vddo gpio tcxo-or function in available on some packages. see section 11.?ordering information? . gpio_7 b7 ? i/o vddo detatch/card_detect uart_rxd d8 d2 i/o vddo uart receive data uart_txd c8 c2 i/o vddo uart transmit data uart_rts_n d7 f2 i/o vddo uart request to send output uart_cts_n e8 e3 i/o vddo uart clear to send input scl f7 e1 i/o vddo i 2 c clock sda e7 d1 i/o vddo i 2 c data
document no. 002-14804 rev. *h page 27 of 50 preliminary cyw20710 spim_clk a8 c1 i/o vddo serial flash spi clock spim_cs_n c7 e2 i/o vddo serial flash active-low chip select pcm_in f6 d4 i/o vddo pcm/i2s data input pcm_out g6 e4 i/o vddo pcm/i2s data output pcm_clk f4 c4 i/o vddo pcm/i2s clock pcm_sync f5 a4 i/o vddo pcm sync/i2s word select coex_in b6 ? i/o vddo coexistence input coex_out0 e4 ? i/o vddo coexistence output coex_out1 e5 ? i/o vddo coexistence output otp_dis ? a2 i/o vddo otp disable pin. by default, leave this pin floating. supplies vddif b1 ? i n/a radio if pll supply vddtf c1 b7 i n/a radio pa supply vddlna e1 ? i n/a radio lna supply vddrf f1 e7 i n/a radio supply vddpx g1 f7 i n/a radio rf pll supply vddc a5 a3 i n/a core logic supply vddc b8 f1 i n/a core logic supply vddc f8 ? i n/a core logic supply vddo g5 d3 i n/a digital i/o supply voltage vddo a6 ? i n/a digital i/o supply voltage vddo g8 ? i n/a digital i/o supply voltage nc ? b1 i n/a no connect vss c2 d7 ? n/a ground vss d2 b6 ? n/a ground vss f2 e6 ? n/a ground vss d3 f6 ? n/a ground vss c6 f3 ? n/a ground vss a7 a1 ? n/a ground vss g7 ? ? n/a ground vss ? b2 ? n/a ground table 8. cyw20710 signal descriptions (cont.) signal fpbga 50-ball wlbga 42-bump i/o power domain description
document no. 002-14804 rev. *h page 28 of 50 preliminary cyw20710 8. ball grid arrays figure 8 shows the top view of the 50-ball 4.5 x 4 x 0.6 mm (fpbga). figure 8. 50-ball 4.5 x 4 x 0.6 mm (fpbga) array figure 9 shows the top view of the 42-bump, 2.97 x 2.46 x 0.5 mm array. figure 9. 42-bump 2.97 x 2.46 x 0.5 mm array (top view) table 9. ball-out for th e 50-ball CYW20710A1KUFBXG 1 2 3 4 5 6 7 8 a vreg vreghv vbat lpo_in vddc vddo vss spim_clk b vddif reg_en gpio_1 rst_n gpio_0 coex_in gpio_7 vddc c vddtf vss ? tm0 ? vss spim_cs_n uart_txd d rfp vss vss ? ? ? uart_rts_n uart_rxd e vddlna ? gpio6 coex_out0 coex_out1 gpio_5 sda uart_cts_n f vddrf vss tm2 pcm_clk pcm_sync pcm_in scl vddc g vddpx xin xout res vddo pcm_out vss vddo g f e d c b a 12345678 f e d c b a 1234567
document no. 002-14804 rev. *h page 29 of 50 preliminary cyw20710 table 10. ball-out for the 42-bump cyw20710a1kubxg 1 2 3 4 5 6 7 a vss otp_dis vddc pcm_sync vbat vreghv vreg b n/c vss gpio_1 lpo_in reg_en vss vddtf c spim_clk uart_txd gpio_0 pcm_clk rst_n tm2 rfp d sda uart_rxd vddo pcm_in gpio_6 res vss e scl spim_cs_n uart_cts_n pcm_out xout vss vddrf f vddc uart_rts_n vss gpio_5 xin vss vddpx
document no. 002-14804 rev. *h page 30 of 50 preliminary cyw20710 9. electrical characteristics note: all voltages listed in table 11 are referenced to v dd . table 11. absolute maximum ratings rating signal\parameter value unit dc supply voltage for rf vdd_rf 1 1. vdd_rf collectively refers to the vddif, vddlna, vddpx, and vddrf rf power supplies. 1.32 v dc supply voltage for core vddc 1.32 v dc supply voltage for i/o vddo 2 2. if vddo is not applied, voltage should never be applied to any digital i/o pins (i/o pins should never be driven or pulled hi gh). the list of digital i/o pins incl udes the following (these pins are listed in section 7.?pin-out and signal descriptions? with vddo shown as their power domain): gpio[3], gpio[5], gpio[6] scl, sda n_mode spim_cs_n, spim_clk 3.6 v dc supply voltage for pa vddtf 3.3 v maximum voltage on input or output pins vimax vddo + 0.3 v minimum voltage on input or output pins vimin vss ? 0.3 v storage temperature tstg ?40 to 125 c table 12. power supply parameter symbol minimum typical maximum unit dc supply voltage for rf vdd_rf 1 1. vdd_rf collectively refers to the vddif, vddlna, vddpx, vddlna, vddrf rf power supplies. 1.159 1.22 1.281 v dc supply noise for rf, from 100 khz to 1 mhz vdd_rf 2 2. overall performance defined using integrated regulation. ??150 v rms dc supply voltage for core vddc 1.159 1.22 1.281 v dc supply voltage for i/o vddo 1.7 ? 3.6 v dc supply vddtf 3 3. vddtf for class 2 must be connected to vreg (main ldo output). vddtf for class 1 must be connected to vreghv (hv ldo output) or an external voltage source. refer to the cypress compatibil ity guide for configuration detail s. vddtf requires a capacitor t o ground. the value of the capacitor must be tuned to ensure optimal rf rx s ensitivity. the typica l capacitor value is 10 pf for both package s. the value may depend on board layout. 1.12 ? 3.3 v
document no. 002-14804 rev. *h page 31 of 50 preliminary cyw20710 note: by default, the drive streng th settings specified in ta b l e 1 5 are for 3.3v. to achieve the required drive strength for a vddio of 2.5v or 1.8v, contact a cypress tec hnical support representative (see ?technical support? for contact information). table 13. high-voltage regulato r (hv ldo) electrical specifications parameter minimum typical maximum unit input voltage 2.3 ? 5.5 v output voltage 1.8 ? 3.3 v max current load ? ? 95 ma load capacitance 1 ? 10 ? f load capacitor esr 0.01 ? 2 ? psrr 20 ? 40 db turn-on time (c load = 2.2 f) ? ? 200 ? s dropout voltage ? ? 200 mv table 14. main regulator (main ldo) electrical specifications parameter minimum typical maximum unit input voltage 1.63 ? 3.63 v output voltage 1.159 1.22 1.281 v load current ? ? 60 ma load capacitance 1 ? 2.2 ? f esr 0.1 ? 0.5 ? turn-on time ? ? 300 ? s psrr 15 ? ? db dropout voltage ? ? 200 mv table 15. digital i/o characteristics characteristics symbol minimum typical maximum unit input low voltage (vddo = 3.3v) v il ??0.8v input high voltage (vddo = 3.3v) v ih 2.0 ? ? v input low voltage (vddo = 1.8v) v il ??0.6v input high voltage (vddo = 1.8v) v ih 1.1 ? ? v output low voltage v ol ??0.4v output high voltage v oh vddo ? 0.4v ? ? v input low current i il ??1.0 ? a input high current i ih ??1.0 ? a output low current (vddo = 3.3v, v ol = 0.4v) i ol ??3.0ma output high current (vddo = 3.3v, v oh = 2.9v) i oh ??3.0ma output low current (vddo = 1.8v, v ol = 0.4v) i ol ??3.0ma output high current (vddo = 1.8v, v oh = 1.4v) i oh ??3.0ma input capacitance c in ??0.4pf
document no. 002-14804 rev. *h page 32 of 50 preliminary cyw20710 table 16. pad i/o characteristics 1 1. all digital i/o internal pull-up or pull-down values are around 60 k ? . i/o pad characteristics pad name pull-up/pull-down fail-safe coex_out0 y y coex_out1 y y coex_in y y pcm_clk y y pcm_out y y pcm_in y y pcm_sync y y uart_rts_n y y uart_cts_n y y uart_rxd y y uart_txd y y gpio_0 y y gpio_1 y y gpio_2 y y gpio_4 y y gpio_7 y y rst_n n/a y otp_dis y n
document no. 002-14804 rev. *h page 33 of 50 preliminary cyw20710 table 17. current consumption?class 1(10 dbm) operational mode conditions typical units receive (1 mbps) current level during receive of a basic rate packet 31 ma transmit (1 mbps) current level during transmit of a basic rate packet, gfsk output power = 10 dbm 65 ma receive (edr) current level during receive of a 2 or 3 mbps rate packet 32 ma transmit (edr) current level during transmit of a 2 or 3 mbps rate packet, gfsk output power = 10 dbm 59 ma dm1/dh1 average current during basic rate max throughput connection which includes only this packet type. 45 ma dm3/dh3 average current during basic rate max throughput connection which includes only this packet type. 46 ma dm5/dh5 average current during max basic rate throughput connection which includes only this packet type. 48 ma hv1 average current during sco voice connection consisting of only this packet type. acl channel is in 500 ms sniff. 38 ma hv2 average current during sco voice connection consisting of only this packet type. acl channel is in 500 ms sniff. 23 ma hv3 average current during sco voice connection consisting of only this packet type. acl channel is in 500 ms sniff. 17 ma hci only active average current when waiting for hci command uart or spi transports. 4.8 ma sleep uart transport active, external lpo clock available. 55 a sleep, hv reg bypass uart transport active, external lpo clock available, hv ldo disabled and in bypass mode. 45 a inquiry scan (1.28 sec) periodic scan rate is 1.28 sec. 350 a page scan (r1) periodic scan rate is r1 (1.28 sec). 350 a inquiry scan + page scan (r1) both inquiry and page scans are interlaced together at 1.28 sec periodic scan rate. 630 a sniff master (500 ms) attempt and timeout parameter s set to 4. quality connection which rarely requires more than minimum packet exchange. 175 a sniff slave (500 ms) attempt and timeout parameter s set to 4. quality connection which rarely requires more than minimum packet exchange. sniff master follows optimal sniff protocol of cyw20710 master. 160 a sniff (500 ms) + inquiry/ page scan (r1) same conditions as sniff master and page scan (r1). scan maybe either inquiry scan or page scan at 1.28 sec periodic scan rate. 455 a sniff (500ms) + inquiry scan + page scan (r1) same conditions as sniff master and inquiry scan + page scan. 760 a
document no. 002-14804 rev. *h page 34 of 50 preliminary cyw20710 table 18. current consumption?class 2 (2 dbm) operational mode conditions typical unit receive (1 mbps) current level during receive of a basic rate packet 31 ma transmit (1 mbps) current level during transmit of a basic rate packet, gfsk output power = 2 dbm 44 ma receive (edr) current level during receive of a 2 or 3 mbps rate packet 32 ma transmit (edr) current level during transmit of a 2 or 3 mbps rate packet, gfsk output power = 2 dbm 41 ma dm1/dh1 average current during basic rate max throughput connection, which includes only this packet type. 35 ma dm3/dh3 average current during basic rate max throughput connection, which includes only this packet type. 36 ma dm5/dh5 average current during max basic rate throughput connection, which includes only this packet type. 37 ma hv1 average current during sco voice connecti on consisting of only this packet type. acl channel is in 500 ms sniff. 28 ma hv2 average current during sco voice connecti on consisting of only this packet type. acl channel is in 500 ms sniff. 17 ma hv3 average current during sco voice connecti on consisting of only this packet type. acl channel is in 500 ms sniff. 13 ma hci only active average current when waiting fo r hci command uart or spi transports. 4.8 ma sleep uart transport active, external lpo clock available. 55 a sleep, hv reg bypass uart transport active, external lpo clock available, hv ldo disabled and in bypass mode. 45 a inquiry scan (1.28 sec) periodic scan rate is 1.28 sec. 350 a page scan (r1) periodic scan rate is r1 (1.28 sec). 350 a inquiry scan + page scan (r1) both inquiry and page scans are interlaced together at 1.28 sec periodic scan rate. 630 a sniff master (500 ms) attempt and timeout parameters set to 4. quality connection which rarely requires more than minimum packet exchange. 145 a sniff slave (500 ms) attempt and timeout paramete rs set to 4. quality connection which rarely requires more than minimum packet exchange. sniff master follows optimal sniff protocol of cyw20710 master. 135 a sniff (500 ms) + inquiry/page scan (r1) same conditions as sniff master and p age scan (r1). scan can be either inquiry scan or page scan at 1.28 sec periodic scan rate. 425 a sniff (500 ms) + inquiry scan + page scan (r1) same conditions as sniff master and inquiry scan + page scan. 730 a table 19. operating conditions parameter conditions minimum typical maximum unit temperature commercial ?30.0 ? 85 c power supply rf, core 1.14 1.22 1.32 v pa supply (vddtf) ? 1.14 2.9 3.3 v
document no. 002-14804 rev. *h page 35 of 50 preliminary cyw20710 9.1 rf specifications table 20. receiver rf specifications 1, 2 parameter conditions minimum typical 3 maximum unit general frequency range ? 2402 ? 2480 mhz rx sensitivity 4 gfsk, 0.1% ber, 1 mbps, fpbga package ? ?89 5 ?85 dbm gfsk, 0.1% ber, 1 mbps, wlbga package ? ?88 5 ?84 dbm ? /4-dqpsk, 0.01% ber, 2 mbps ? ?91 5 ?85 dbm 8-dpsk, 0.01% ber, 3 mbps fpbga package ??86 5 ?81 dbm 8-dpsk, 0.01% ber, 3 mbps, wlbga package ??85 5 ?80 dbm maximum input gfsk, 1 mbps ? ? ?20 dbm maximum input ? /4-dqpsk, 8-dpsk, 2/3 mbps ? ? ?20 dbm interference ? performance c/i cochannel gfsk, 0.1% ber ? ? 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ? 0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ? ?30.0 db c/i > 3 mhz adjacent channel gfsk, 0.1% ber ? ? ?40.0 db c/i image channel gfsk, 0.1% ber ? ? ?9.0 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ? ?20.0 db c/i cochannel ? /4-dqpsk, 0.1% ber ? ? 13 db c/i 1 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? 0 db c/i 2 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? ?30.0 db c/i > 3 mhz adjacent channel 8- dpsk, 0.1% ber ? ? ?40.0 db c/i image channel ? /4-dqpsk, 0.1% ber ? ? ?7.0 db c/i 1 mhz adjacent to image channel ? /4-dqpsk, 0.1% ber ? ? ?20.0 db c/i cochannel 8-dpsk, 0.1% ber ? ? 21 db c/i 1 mhz adjacent channel 8-dpsk, 0.1% ber ? ? 5 db c/i 2 mhz adjacent channel 8-dpsk, 0.1% ber ? ? ?25.0 db c/i > 3 mhz adjacent channel 8- dpsk, 0.1% ber ? ? ?33.0 db c/i image channel 8-dpsk, 0.1% ber ? ? 0 db c/i 1 mhz adjacent to image channel 8-dpsk, 0.1% ber ? ? ?13.0 db out-of-band ? blocking ? performance ? (cw) ? 6 30 mhz?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm
document no. 002-14804 rev. *h page 36 of 50 preliminary cyw20710 out-of-band ? blocking ? performance, ? modulated ? interferer 776?764 mhz cdma ? ?15 ? dbm 824?849 mhz cdma ? ?15 ? dbm 1850?1910 mhz cdma ? ?20 ? dbm 824?849 mhz edge/gsm ? ?10 ? dbm 880?915 mhz edge/gsm ? ?10 ? dbm 1710?1785 mhz edge/gsm ? ?15 ? dbm 1850?1910 mhz edge/gsm ? ?15 ? dbm 1850?1910 mhz wcdma ? ?25 ? dbm 1920?1980 mhz wcdma ? ?25 ? dbm intermodulation ? performance ? 7 bt, df = 5 mhz ? ?39.0 ? ? dbm spurious ? emissions ? 8 30 mhz to 1 ghz ? ? ? ?57 dbm 1 ghz to 12.75 ghz ? ? ? ?47 dbm 65 mhz to 108 mhz fm rx ? ?145 ? dbm/hz 746 mhz to 764 mhz cdma ? ?145 ? dbm/hz 851?894 mhz cdma ? ?145 ? dbm/hz 925?960 mhz edge/gsm ? ?145 ? dbm/hz 1805?1880 mhz edge/gsm ? ?145 ? dbm/hz 1930?1990 mhz pcs ? ?145 ? dbm/hz 2110?2170 mhz wcdma ? ?145 ? dbm/hz 1. all specifications are singl e ended. unused inputs are left open. 2. all specifications, except typical, are for industrial temperatures. for details see table 19 . 3. typical operating conditions are 1.22v operating voltage and 25c ambient temperature. 4. the receiver sensitivity is measured at ber of 0.1% on the device interface. 5. measured with the dirty transmitter off. typically, there is approximately 1 db less in rx sensitivity when the dirty transmi tter is on. 6. meets this specification using front-end band pass filter. 7. f0 = -64 dbm bluetooth-modulated signal, f1 = ?39 dbm sine wa ve, f2 = ?39 dbm bluetooth-modulated signal, f0 = 2f1 ? f2, and |f2 ? f1| = n*1 mhz, where n is 3, 4, or 5. for the typical case, n = 5. 8. includes baseband radiated emissions. table 20. receiver rf specifications 1, 2 (cont.) parameter conditions minimum typical 3 maximum unit
document no. 002-14804 rev. *h page 37 of 50 preliminary cyw20710 table 21. transmitter rf specifications 1, 2 1. all specifications ar e for industrial temperatures. for details, see table 19 . 2. all specifications are singl e-ended. unused input are left open. parameter conditions minimum typical maximum unit general frequency range ? 2402 ? 2480 mhz class1: gfsk tx power 3 3. +10 dbm output for gfsk measured with vddtf = 2.9 v. ?6.510?dbm class1: edr tx power 4 4. +8 dbm output for edr measured with vddtf = 2.9 v. ?4.58?dbm class 2: gfsk tx power ? ?1.5 2 ? dbm power control step ? 2 4 6 db modulation accuracy p/4-dqpsk frequency stability ? ?10 ? 10 khz p/4-dqpsk rms devm ? ? ? 20 % p/4-qpsk peak devm ? ? ? 35 % p/4-dqpsk 99% devm ? ? ? 30 % 8-dpsk frequency stability ? ?10 ? 10 khz 8-dpsk rms devm ? ? ? 13 % 8-dpsk peak devm ? ? ? 25 % 8-dpsk 99% devm ? ? ? 20 % in-band spurious emissions +500 khz ? ? ? ?20 dbc 1.0 mhz < |m ? n| < 1.5 mhz ? ? ? ?26 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ? ? ?20 dbm |m ? n| > 2.5 mhz ? ? ? ?40 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 5 5. maximum value is the value r equired for bluetooth qualification. dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 5, 6 6. meets this spec using a front-end bandpass filter. dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm gps band noise emission (without a front-end band pass filter) 1572.92 mhz to 1577.92 mhz ? ? ?150 ?127 dbm/hz out-of-band noise emissions (without a front-end band pass filter) 65 mhz to 108 mhz fm rx ? ?145 ? dbm/hz 746 mhz to 764 mhz cdma ? ?145 ? dbm/hz 869 mhz to 960 mhz cdma ? ?145 ? dbm/hz 925 mhz to 960 mhz edge/gsm ? ?145 ? dbm/hz 1805 mhz to 1880 mhz edge/gsm ? ?145 ? dbm/hz 1930 mhz to 1990 mhz pcs ? ?145 ? dbm/hz 2110 mhz to 2170 mhz wcdma ? ?145 ? dbm/hz
document no. 002-14804 rev. *h page 38 of 50 preliminary cyw20710 9.2 timing and ac characteristics in this section, use the numbers listed in the re ference column to interp ret the timing diagrams. 9.2.1 startup timing there are two basic startup scenarios. in one scenario, the chip startup and firmware boot is held off while the rst_n pin is a sserted. in the second scenario, the chip startup and firmware boot is di rectly triggered by the chip power-up. in this case, an interna l power- on reset (por) is held fo r a few ms, after which the chip commences startup. the global reset signal in the cyw20710 is a logical or (actually a wired and, since the signals are active low) of the rst_n i nput and the internal por signals. the last signal to be released dete rmines the time at which the chip is released from reset. the por is typically asserted for 3 ms after vddc crosses the 0.8v th reshold, but it may be as soon as 1.5 ms after this event. after the chip is released from reset, both startup scenarios follow the same sequence, as follows: 1. after approximately 120 s, the clk_req (gpio_5) signal is asserted. 2. the chip remains in sleep state for a minimum of 4.2 ms. 3. if present, the tcxo and lpo clocks must be o scillating by the end of the 4.2 ms period. if a tcxo clock is not in the system, a crystal is assumed to be present at the xin and xout pins. if an lpo clock is not used, the firmware will detect the absence of a clock at the lp o_in lead and use the internal lpo clock instead. figure 10 and figure 11 illustrate the two startup timing scenarios. figure 10. startup timing from rst_n figure 11. startup timing from power-on reset vddio, vbat,reg_en* vddc > 0.8v t max = 4.2 m s vreg rst_n gpio5 (clk_req) tcxo lpo t = 6 4 to 1 71 s t = 3 0 0 s t rampmax = 200 s vddio, vbat,reg_en* vddc > 0.8v t max = 4.2 ms gpio5 (clk_req) t min = 1.5 ms vreg tcxo lpo internal por t rampmax = 200 s t = 300 s t = 64 to 171 s
document no. 002-14804 rev. *h page 39 of 50 preliminary cyw20710 9.2.2 uart timing figure 12. uart timing table 22. uart timing specifications reference characteristics minimum maximum unit 1 delay time, uart_cts_n low to uart_txd valid ? 24 baudout cycles 2 setup time, uart_cts_n high before midpoint of stop bit ? 10 ns 3 delay time, midpoint of stop bit to uart_rts_n high ? 2 baudout cycles 1 3 2 uart_cts_n uart_txd uart_rxd uart_rts_n midpoint of stop bit midpoint of stop bit
document no. 002-14804 rev. *h page 40 of 50 preliminary cyw20710 9.2.3 pcm interface timing figure 13. pcm interface timing (short frame synchronization, master mode) table 23. pcm interface timing specifications (short frame synchronization, master mode) reference characteristics minimum maximum unit 1 pcm bit clock frequency 128 2048 khz 2 pcm bit clock high time 128 ? ns 3 pcm bit clock low time 209 ? ns 4 delay from pcm_bclk rising edge to pcm_sync high ? 50 ns 5 delay from pcm_bclk rising edge to pcm_sync low ? 50 ns 6 delay from pcm_bclk rising edge to data valid on pcm_out ? 50 ns 7 setup time for pcm_in before pcm_bclk falling edge 50 ? ns 8 hold time for pcm_in after pcm_bclk falling edge 10 ? ns 9 delay from falling edge of pcm_bclk during last bit period to pcm_out becoming high impedance ?50ns 1 2 3 4 5 6 7 8 pcm_bclk pcm_sync pcm_out pcm_in bit 15 (previous frame) bit 15 (previous frame) bit 0 bit 0 bit 15 bit 15 9 high impedence
document no. 002-14804 rev. *h page 41 of 50 preliminary cyw20710 figure 14. pcm interface timing (short frame synchronization, slave mode) table 24. pcm interface timing specificatio ns (short frame synchronization, slave mode) reference characteristics minimum maximum unit 1 pcm bit clock frequency 128 2048 khz 2 pcm bit clock high time 209 ? ns 3 pcm bit clock low time 209 ? ns 4 setup time for pcm_sync before falling edge of pcm_bclk 50 ? ns 5 hold time for pcm_sync after falling edge of pcm_bclk 10 ? ns 6 hold time of pcm_out after pcm_bclk falling edge ? 175 ns 7 setup time for pcm_in before pcm_bclk falling edge 50 ? ns 8 hold time for pcm_in after pcm_bclk falling edge 10 ? ns 9 delay from falling edge of pcm_bclk during last bit period to pcm_out becoming high impedance ? 100 ns 1 2 3 4 5 6 7 8 pcm_bclk pcm_sync pcm_out pcm_in bit 0 bit 0 bit 15 bit 15 bit 15 (previous frame) bit 15 (previous frame) high impedence 9
document no. 002-14804 rev. *h page 42 of 50 preliminary cyw20710 figure 15. pcm interface timing (long frame synchronization, master mode) table 25. pcm interface timing specificatio ns (long frame synchronization, master mode) reference characteristics minimum maximum unit 1 pcm bit clock frequency 128 2048 khz 2 pcm bit clock high time 209 ? ns 3 pcm bit clock low time 209 ? ns 4 delay from pcm_bclk rising edge to pcm_sync high during first bit time ?50ns 5 delay from pcm_bclk rising edge to pcm_sync low during third bit time ?50ns 6 delay from pcm_bclk rising edge to data valid on pcm_out ? 50 ns 7 setup time for pcm_in before pcm_bclk falling edge 50 ? ns 8 hold time for pcm_in after pcm_bclk falling edge 10 ? ns 9 delay from falling edge of pcm_bclk during last bit period to pcm_out becoming high impedance ?50ns 1 2 3 4 5 6 7 8 pcm_bclk pcm_sync pcm_out pcm_in bit 0 bit 0 bit 1 bit 1 bit 2 bit 2 bit 15 bit 15 high impedence 9
document no. 002-14804 rev. *h page 43 of 50 preliminary cyw20710 figure 16. pcm interface timing (long frame synchronization, slave mode) table 26. pcm interface timing specificatio ns (long frame synchronization, slave mode) reference characteristics minimum maximum unit 1 pcm bit clock frequency. 128 2048 khz 2 pcm bit clock high time. 209 ? ns 3 pcm bit clock low time. 209 ? ns 4 setup time for pcm_sync before falling edge of pcm_bclk during first bit time. 50 ? ns 5 hold time for pcm_sync after falling edge of pcm_bclk during second bit period. (pcm_sync may go low any ti me from second bit period to last bit period). 10 ? ns 6 delay from rising edge of pcm_bclk or pcm_sync (whichever is later) to data valid for first bit on pcm_out. ?50ns 7 hold time of pcm_out after pcm_bclk falling edge. ? 175 ns 8 setup time for pcm_in before pcm_bclk falling edge. 50 ? ns 9 hold time for pcm_in after pcm_bclk falling edge. 10 ? ns 10 delay from falling edge of pcm_bclk or pcm_sync (whichever is later) during last bit in slot to pcm_out becoming high impedance. ? 100 ns 1 2 3 45 7 8 9 pcm_bclk pcm_sync pcm_out pcm_in bit 0 bit 1 bit 0 bit 1 bit 15 bit 15 6 high impedence 10
document no. 002-14804 rev. *h page 44 of 50 preliminary cyw20710 9.2.4 bsc interface timing figure 17. bsc interface timing diagram table 27. bsc interface timing specifications reference characteristics minimum maximum unit 1 clock frequency ? 100 400 800 1000 khz 2 start condition setup time 650 ? ns 3 start condition hold time 280 ? ns 4 clock low time 650 ? ns 5 clock high time 280 ? ns 6 data input hold time 1 1. as a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of scl to avoid unintended g eneration of start or stop conditions 0? ns 7 data input setup time 100 ? ns 8 stop condition setup time 280 ? ns 9 output valid from clock ? 400 ns 10 bus free time 2 2. time that the cbus must be free before a new transaction can start. 650 ? ns 2 3 4 5 6 78 9 10 scl sda in sda out 1
document no. 002-14804 rev. *h page 45 of 50 preliminary cyw20710 10. mechanical information figure 18. CYW20710A1KUFBXG mechanical drawing
document no. 002-14804 rev. *h page 46 of 50 preliminary cyw20710 figure 19. 42-bump cyw20710a1kubxg me chanical drawing
document no. 002-14804 rev. *h page 47 of 50 preliminary cyw20710 10.1 tape, reel, and packing specification figure 20. reel, labeling , and packing specification ? ? ? ? b r o a d c o m b a r c o d e esd warning device orientation/mix lot number each reel may contain up to three lot numbers , independent of the date code . individual lots must be labeled on the box , moisture barrier bag, and the reel. moisture barrier bag contents/label desiccant pouch (minimum 1) humidity indicator (minimum 1) reel (maximum 1) pin 1 top-right corner toward sprocket holes.
document no. 002-14804 rev. *h page 48 of 50 preliminary cyw20710 11. ordering information the following table lists available part numbers and describes diff erences in package type, available i/o, and functional confi guration. see the referenced figures and tables for me chanical drawings and package i/o information. all packages are rated from ?30c to +85c. 12. additiona l information 12.1 acronyms and abbreviations in most cases, acronyms and abbreviations are defined upon first use. for a more complete list of acronyms and other terms used in cypress documents, go to: http://www.cypress.com/glossary. 12.2 iot resources cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( https://community.cypress.com/ ) part number package type functional i/o features strapped configuration CYW20710A1KUFBXG commercial 50-ball fpbga, 4.5 mm x 4.0 mm x 0.6 mm. see figure 18 . dedicated coex 1 , more gpio, tm0 2 table 9 1. all packages support coexis tence features through the ability to re-purpose most digital i/o based on the desired user config uration. package include balls coexistence functi onality (default). 2. tm0 allows configuration of clk_req output polarity. tcxo and/or mode enabled cyw20710a1kubxg commercial 42-bump wlbga, 3.02 mm x 2.51 mm x 0.55 mm. see figure 19 . table 10 tcxo and/or mode enabled
document no.002-14804 rev. *h page 49 of 50 preliminary cyw20710 document history page document title: cyw20710 single-chip bluetooth? transceiver and baseband processor document number: 002-14804 revision ecn orig. of change submission date description of change ** - - 6/09/2010 20710-ds100-r initial release *a - - 6/23/2010 20710-ds100-r updated: ? ?programming?. ? ?frequency selection? on page 37 by adding 24 mhz as a reference frequency. ? table 9: ?ball-out for the 42-bump cyw20710a0kubxg?. *b - - 8/16/2010 20710-ds102-r updated: ? table 10: ?absolute maximum voltages? ? table 11: ?power supply? ? table 13: ?main regulator (main ld o) electrical specifications? *c - - 2/16/2010 20710-ds103-r updated: ? part numbers changed to CYW20710A1KUFBXG (50-ball fpbga) and cyw20710a1kubxg (42-ball wlbga) throughout the document *d - - 7/28/2011 20710-ds104-r updated: ? ?simultaneous uart transport and bridging? (removed) ? changed ?ufbga? to ?fpbga? throughout. *e - - 10/17/2011 20710-ds105-r updated: ? table 20: ?transmitter rf specifications? *f - - 12/16/2011 20710-ds107-r updated: ? table 7: ?cyw20710 signal descriptions? ? table 10: ?absolute maximum ratings? ? table 17: ?current consum ption ? class 2 (2 dbm)? ? table 18: ?operating conditions? ? table 19: ?receiver rf specifications? *g - - 10/4/2013 20710-ds107-r ? updated: ? ?uart interface? ? ?external frequency reference? ? table15. ?digital i/o characteristics" ? figure 10. ?startup timing from rst_n ? figure 11. ?startup timing from power-on reset *h 5484548 utsv 11/25/2016 added cypress part numbering scheme and mapping table on page 1. updated to cypress template.
document no. 002-14804 rev. *h revised november 25, 2016 page 50 of 50 preliminary cyw20710 ? cypress semiconductor corporation, 2010-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desig n, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended us es"). a critical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete lis t of cypress trademarks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 50

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